The present invention relates, in general, to semiconductor devices, and more particularly, to insulated gate semiconductor devices.
Generally, portable communications equipment, as well as portable computers, use low voltage and low power electronic components to conserve power, weight, and size, thereby increasing their portability. In an effort to lower power consumption, the electronic components in these types of systems are designed to operate at supply voltages of less than 5 volts(V). Typically, device parameters such as drain current, threshold voltage, threshold voltage sensitivity, body effect, subthreshold leakage currents, parasitic source/drain capacitances, and source to drain punchthrough voltages limit the operation of insulated gate semiconductor devices at voltages less than 5 volts. Moreover, techniques that improve some device parameters tend to degrade other device parameters. For example, threshold voltage control and the source to drain punchthrough voltages are improved by increasing the dopant concentration between the source and drain regions of the insulated gate semiconductor devices; however, the increased dopant concentration adversely affects the drain current, the body effect, and parasitic source/drain capacitances.
One technique for providing punchthrough protection includes tailoring the dopant concentration profiles near the source and drain regions such that a lateral component of the dopant concentration profiles of these regions has a sufficient dopant concentration to prevent punchthrough while providing a low threshold voltage. Another technique is to increase the doping concentration of the substrate, i.e., the dopant well. However, these techniques typically reduce carrier mobility, thereby lowering the drain current.
Accordingly, it would be advantageous to have an insulated gate semiconductor device and a method for fabricating the insulated gate semiconductor device that improves control of the threshold voltage and increases source/drain to substrate breakdown voltages while providing higher drain current. It would be of further advantage for the method to reduce parasitic source/drain capacitances. Further, the method should be simple and capable of integration into insulated gate semiconductor device process flows.